PHY/SERDES Lead

What We’re Looking For:

 

We’re looking for a PHY/SERDES Lead to own and lead the development of our semi-custom optical PHY layer. 

 

Ideal Background:

 

• Multiple successful tapeouts of SERDES or PHY macros (not necessarily only chiplet interfaces, SERDES also counts here)
• Deep understanding of tradeoffs between XSR/VSR/LR class SERDES and different operating regimes and challenges
• Understanding and ownership of end to end link definition and architecture
• Experience with bringup of PHYs
• Understanding of the integration of PHYs into the system level

Strongly Preferred:

 

• Deep knowledge of and hands-on with chiplet interfaces like UCIe or BoW 
• Deep knowledge and hands-on execution of optical interconnect PHY layers
• Knowledge of re-driven and re-timed PHY interfaces
• Experience with customization of PHYs