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Focus areas include but are not limited to: synthesis, STA, timing closure, place & route and/or sign-off.
Prospective team members require strong Verilog/SystemVerilog; STA expertise; SDC; synthesis/STA tools preferred.
Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role.
Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.
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